(N657) | ASIC Verification ENGINEER ( IP OR UVM )

(N657) | ASIC Verification ENGINEER ( IP OR UVM )

15 ott
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Milano Provincia

15 ott

noreply

Milano Provincia

Skytechnology srl è una società di ingegneria operante nell'area dei sistemi embedded per le aziende nei settori telecomunicazioni, automotive, avionica, aerospazio, trasporti, elettromedicale e industria



Organizzata in tre linee di progettazione (Hardware/FPGA, Software e Firmware, Test e Simulazione), Skytechnology ha la sedi a Milano , Torino e Roma



Ulteriori informazioni sulla nostra società all'indirizzo



www.skytechnology.it



Per progetto per prestigiosa società Telco  stiamo cercando un



ASIC Verification ENGINEER ( IP OR UVM ):



In order of strengthening our technical structure in Milan, we are looking for the following figure:



a)    Senior IP ASIC Verification engineer





b)    Senior UVM Verification engineer



REQUIREMENTS REQUIRED:



a)    Degree in Electronic Engineering, or equivalent



b)    Good knowledge of digital electronics,



c)     Good knowledge and proven experience regarding the main problems of verification ASIC integrated circuits.



Senior IP ASIC Verification engineer



We are looking for senior IP ASIC Verification engineer for some of most important clients.



The candidate will be responsible for the entire verification ASIC flow according to the customer verification process. He/she will be part of the R&D; team for the verification of circuits.



Activities



The activity consists of IP ASIC verifications with a constrained driven methodology



SPECIFIC REQUIREMENTS REQUIRED:



d)    Good knowledge of the most important tools such as Cadence, Specman



e)    Excellent knowledge and proven experience regarding the use of the main laboratory equipment.



f)      Good knowledge of English



g)    it will be a preferential title previous experience with Amba bus and memory interfaces



Senior UVM Verification engineer



We are looking for senior UVM Verification engineer for some of most important clients.



The candidate will be responsible for the entire verification ASIC flow according to uVM and System Verilog verification process. He/she will be part of the R&D; team for the verification of circuits.



Activities



The activity consists of Digital IP level and Soc System level verifications with a uVM and System Verilog methodology



SPECIFIC REQUIREMENTS REQUIRED:



a)    Good knowledge of the most important tools such as Synopsis, Cadence, System Verilog



b)    Excellent knowledge and proven experience regarding the use of the main laboratory equipment.



c)     Good knowledge of English



d)    it will be a preferential title previous experiences with Amba bus, memory interfaces and STM32.



SEDE CATANIA

Puoi trovare l'offerta di lavoro originale su Kit Lavoro:
https://www.kitlavoro.it/lavoro/18669235/n657-asic-verification-engineer-uvm-milano-provincia/?utm_source=html

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