Experteer Overview In this role you will lead the Analog Layout team within NXP's Industrial & Io T edge division, delivering high-performance MCU and analog/Digital ICs. You will collaborate with analog, mixed-signal, and software teams to optimize interfaces and system performance for SOCs. You'll drive digital sub-circuit development, verification, and DFT, ensuring on-time delivery and product quality. The position offers impact in a fast-paced, global R&D; environment focused on edge AI at scale and high-quality, world-class ICs. Retribuzione / Benefits Develop digital sub-circuits for SOCs using RTL (Verilog/System Verilog), including synthesis, STA, formal verification, and power analysis Contribute to DFT implementation and verification and perform debugging Collaborate with analog, mixed-signal,



and software teams to define interfaces and optimize performance Follow team design methodologies to meet schedules and quality targets Perform design verification via simulation, formal techniques, and hardware emulation Participate in post-silicon validation and debugging to ensure product quality Create design documentation, test plans, and design reviews Stay updated on industry trends and best practices in digital IC design methodologies Responsabilità Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field Expertise in Verilog/System Verilog for RTL design and verification Familiarity with EDA tools for RTL coding and synthesis, STA, formal verification Understanding of digital circuit design, timing analysis, power integrity, and low-power techniques Basic knowledge of UVM is a plus Problem-solving attitude, attention to detail, team-oriented mindset #J-18808-Ljbffr

📌 Junior digital design engineer (Italia)
🏢 Experteer Italy
📍 Italia