Digital Verification Engineer
The position is aimed at a Digital Verification engineer with previous experience in digital verification of ASIC.
The position is open on both Castelletto (Italy) and Toulouse (France) sites.
Responsibilities
The candidate will be part of the digital verification team of MEMSs GROUP and will have the opportunity to follow the entire ASIC verification process from specification definition up to final product industrialization.
Responsibilities include definition and development of verification testbench, development of verification components, development of DSP models and digital control logic, test case development for simulation, debugging failures, and creating simulation cases for various scenarios.
Skills & Experience
The preferred seniority is 3 to 5 years of experience.
Background in digital verification testbench (Universal Verification Methodology and System Verilog), knowledge of System Verilog, and experience with digital simulator tools.
Knowledge of Universal Verification Methodology,



System Verilog Assertion, coverage, self?checking capabilities, testbench automation, bug analysis, and reporting.
Basic knowledge of Python scripts, TCL scripts, and version control systems.
Knowledge of formal verification and communication protocols (e.g., I2C, SPI, I3C) is a plus.
Soft skills such as good communication, fluency in English, teamwork, and collaboration across the entire MEMSs GROUP Design team.
EEO Statement
At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning.
#J-*****-Ljbffr

📌 Mems Digital Verification (Bardi)
🏢 Altro
📍 Bardi