02 ago
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Fondazione Chips-IT
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Cascina Priora
02 ago
Fondazione Chips-IT
Cascina Priora
ph3About Fondazione Chips-IT /h3 pFoundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal centre of the Italian semiconductor ecosystem and expertise. /p h3Missions Of The Foundation /h3 ul liPromote the design and development of integrated circuits /li liStrengthen the system of professional training in the field of microelectronics /li liEnsure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field /li /ul h3Posizione /h3 pWe are seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape‑out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna. /p h3Key Responsibilities /h3 ul liDefine and implement verification strategies at IP and SoC levels. /li liDevelop and maintain UVM-based verification environments, including testbenches and functional coverage. /li liDesign and execute test plans aligned with design specifications and requirements. /li liDebug RTL and simulation issues using advanced tools and techniques. /li liIntegrate verification components and ensure complete test coverage. /li liContribute to regression infrastructure and manage automated test execution. /li liCollaborate closely with RTL designers,
DFT engineers, and physical implementation teams. /li liSupport post‑silicon bring‑up and validation activities as needed. /li /ul h3Requisiti /h3 ul liMaster’s degree in Electrical Engineering, Computer Engineering, or a related field. /li liAt least 5 years of experience in digital design verification. /li liStrong knowledge of SystemVerilog and UVM methodology. /li liHands‑on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi). /li liFamiliarity with industry‑standard protocols such as AMBA AXI, APB, and AHB. /li liExperience in writing constrained‑random testbenches and analyzing coverage metrics. /li liGood understanding of digital design, SoC architecture, and RTL development. /li liStrong teamwork, communication, and documentation skills. /li /ul h3Altre Informazioni /h3 pWHAT WE OFFER: /p ul liCompetitive compensation and contract type, to be negotiated based on qualifications and experience. /li liPossibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title. /li liLunch tickets. /li liPrivate health care coverage depending on your role and contract. /li liStructured growth path, with ongoing access to training and updates. /li liNetworking opportunities with industry‑leading professionals. /li liInternational environment. /li liHybrid work policy. /li liTax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years. /li /ul pIn conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro 25.000,00 e 55.000,00. L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all’effettiva esperienza e alle competenze del candidato, e sarà integrata dai vantaggi aziendali previsti per il ruolo. /p /p #J-18808-Ljbffr
📌 Design Verification Engineer SoC (Cascina Priora)
🏢 Fondazione Chips-IT
📍 Cascina Priora