Lead Digital Verification Architect For Socs/Asic (Pavia)

Lead Digital Verification Architect For Socs/Asic (Pavia)

01 ago
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Infineon Technologies
|
Pavia

01 ago

Infineon Technologies

Pavia

Infineon Technologies AG is seeking a Principal Engineer in Functional Digital Design Verification to lead the verification of complex digital and mixed-signal designs, including IPs, subsystems, ASICs and SoCs. You will coordinate planning, tracking, and reporting, and collaborate across teams to ensure verification quality. You will actively contribute hands-on verification, drive improvements, and mentor junior engineers to advance verification methodologies and efficiency across multi-site #J-*****-Ljbffr

📌 Lead Digital Verification Architect For Socs/Asic (Pavia)
🏢 Infineon Technologies
📍 Pavia

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