pExperteer Italy is seeking a Mixed Signal Verification engineer in Catania to verify analog/mixed-signal IPs and build SV Real Number and Verilog-AMS models for analog blocks.
You will collaborate with designers and systems engineers to validate architecture, test modes, and DFT strategies with focus on robust verification.
/ppThe role requires a strong background in analog and mixed-signal fundamentals, proficiency in Verilog/SystemVerilog/Verilog-AMS/Verilog-A, and 2+ years of related experience, /p #J-*****-Ljbffr
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