Experteer Overview Join Marvell's CE-OPHY team to design high-speed analog blocks and complete IPs for optical transceivers used in data centers and telecom networks. You will own macro-level designs, mentor junior designers, and collaborate across functions to push performance and power efficiency in next-generation transceivers. This role places you at the core of submicron process design, tackling real-time data challenges at multi‐GHz speeds. You'll contribute to Marvell's reputation for market-leading optical PHY solutions in a fast‐paced, collaborative environment.
Retribuzione / Benefits Analyze block specifications and select suitable topologies
Design analog blocks at transistor level
Supervise layout activities, provide guidelines, and conduct post-layout verifications
Model blocks and validate models
Collaborate with other teams to enhance existing solutions
Take responsibility for designing entire analog macros or IPs
Participate in cross‐functional meetings and interact with other functions
Train and mentor junior designers
Responsabilità Master's degree in Electrical Engineering or PhD in Electrical Engineering (microelectronics preferred) with 10+ years (Master) or 7+ years (PhD) of relevant experience
Proven experience in independently designing ICs from architecture to lab characterization with full macro/IP ownership
Strong analog design skills, preferably in multi‐GHz range
Extensive experience in analog custom layout supervision
Familiarity with EDA CAD tools
Experience in IC performance measurement and correlating simulations with measurements
Direct project experience in multi‐Gbps electrical SerDes or electro‐optical transceivers or advanced CMOS nodes (FinFET) preferred
Strong communication, presentation, and documentation skills
Proficiency in Italian and English (min B2)
Requisiti fondamentali Competitive compensation
Great benefits
Collaborative environment
Inclusive culture
Growth and development opportunities
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📌 Analog Design Engineer, Principal (Italia)
🏢 Altro
📍 Italia
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