Experteer Italy is seeking a Mixed Signal Verification engineer in Catania to verify analog/mixed-signal IPs and build SV Real Number and Verilog-AMS models for analog blocks. You will collaborate with designers and systems engineers to validate architecture, test modes, and DFT strategies with focus on robust verification.
The role requires a strong background in analog and mixed-signal fundamentals, proficiency in Verilog/SystemVerilog/Verilog-AMS/Verilog-A, and 2+ years of related experience, #J-18808-Ljbffr
📌 Mixed-Signal Verification Engineer — AI-Edge, Equity (Catania)
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📍 Catania
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