Job description:

Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
Define digital subsystem architectures
Lead RTL development and integration
Drive design reviews and quality standards
Support verification and implementation teams
Mentor design engineers

Profile description:

MSc or PhD in Electrical Engineering
10+ years digital IC design experience
RTL design (Verilog/SystemVerilog)
High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage
Interface protocols and clock-domain crossing
Synthesis and timing analysis
Advanced CMOS node experience,



including FinFET and/or FD-SOI, is required

We offer:

ams OSRAM is an Equal Employment Opportunity Employer. Diversity, equity and inclusion is strongly established in our corporate culture and we firmly believe it makes us more successful as a company. All qualified applications will receive consideration for employment regardless of ethnic, national or social origin, gender, gender identity, sexual orientation, color, religion, age, physical and mental abilities.

Stefanie Kleierl
[email protected]
Find out more about us at: www.ams-osram.com

📌 Principal HS Digital Design Engineer (Pavia)
🏢 ams OSRAM
📍 Pavia