Principal Physical Digital Design Engineer (Pavia)

Principal Physical Digital Design Engineer (Pavia)

17 ago
|
Fondazione Chips-IT
|
Pavia

17 ago

Fondazione Chips-IT

Pavia

About Fondazione Chips-IT
*The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.*
*The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.*
Missions Of The Foundation
- Promote the design and development of integrated circuits
- Strengthen the system of professional training in the field of microelectronics
- Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

Posizione
The Chips-IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System-on-Chic (SoC)



development programs. The position will contribute to cutting-edge R&D; activities, working closely with architecture, RTL, verification, and technology teams in a state-of-the-art microelectronics design environment. The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes. The role requires deep hands-on expertise across the full physical implementation lifecycle, from netlist handoff through place & route, signoff, and tape-out, while also providing technical mentorship and driving best practices within the design team.

The work can be carried out either in Pavia or in Bologna.

Key Responsibilities
- Lead and execute end-to-end physical design flows for complex SoCs and IP blocks, from RTL handoff to GDSII.
- Collaborate closely with RTL, verification, DFT, and architecture teams to resolve design and impl

📌 Principal Physical Digital Design Engineer (Pavia)
🏢 Fondazione Chips-IT
📍 Pavia

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