ph3The Role /h3 pAs a bPhysical Design Senior Engineer /b, you will take technical ownership of the implementation for highly complex digital blocks, including high-speed interfaces, mixed-signal control logic, and automotive low-power modules.
Working at the intersection of logic and physics, you are responsible for ensuring that the functional design intent is fully preserved while being highly optimized during the physical implementation phase.
/p h3Key Responsibilities /h3 ul liAdvanced Physical Implementation Constraint Ownership /li liFull-Flow Execution: Take technical ownership of the RTL-to-GDSII implementation, including Floorplanning, Place and Route (PR), and Clock Tree Synthesis (CTS).
/li liExecution Strategy: Drive a "constraint-driven" approach to minimize iterations and ensure optimal physical results.
/li liBottleneck Resolution: Analyze functional contexts to identify and resolve routing congestion and timing bottlenecks proactively.
/li liConstraint Maintenance: Hands-on management of SDC constraints at every stage; responsible for cleaning, regenerating, and validating timing constraints to ensure they reflect silicon reality (e.g., Multi-Cycle Paths, False Paths).
/li liTiming Closure ECO Implementation /li liSign-off Focus: Deliver complex timing closure for designs with multiple clock domains and asynchronous interfaces using DMSA and OCV/AOCV/POCV techniques.
/li liAdvanced ECO Execution: Implement Engineering Change Orders (ECO) at the gate level and propose physical-level adjustments when required to meet timing or power targets.
/li liDesign Integrity:



Perform and validate Signal Integrity (SI) and Power Integrity (IR-Drop/EM) analyses to ensure robust sign-off.
/li /ul h3Requirements (Must Have) /h3 ul liExperience: 10+ years of professional experience in Semiconductor Physical Design and Digital Implementation.
/li liSDC Expertise: Expert knowledge of SDC format with the ability to write, debug, and manage complex constraints for Multi-Mode Multi-Corner (MMMC) designs.
/li liTiming STA: Solid hands-on experience with STA tools (PrimeTime or Tempus) and managing violations in advanced technology nodes or critical environments (e.g., Automotive).
/li liCDC Knowledge: Proficiency in Clock Domain Crossing (CDC) analysis and verification.
/li liAutomation Skills: Excellent scripting capabilities (Tcl, Python, or Perl) for flow automation and report analysis.
/li /ul h3Preferred Qualifications (Nice To Have) /h3 ul liRTL-to-GDSII Integration: Proven experience interfacing with Front-End teams to optimize RTL for better physical synthesis and routability.
/li liManufacturing Reliability: Practical experience implementing DFM (Design for Manufacturing) rules and performing Yield analysis to ensure high-volume production stability.




/li liAdvanced Power Methodologies: Hands-on experience with Low Power design flows using UPF or CPF, including the implementation of power-gating and multi-voltage domains.
/li liDomain-Specific Compliance: Familiarity with Automotive safety standards (ISO *****), specifically regarding physical redundancy or electromigration (EM) requirements for mission-critical chips.
/li liHierarchy Partitioning: Experience managing large-scale hierarchical designs, including partitioning and top-level integration challenges.
/li /ul h3What Do We Offer?
/h3 ul liJoin a highly innovative microelectronics company working at the forefront of RISC-V and advanced SoC technologies.
/li liOpportunity to play a key technical leadership role bridging industry and public research.
/li liCollaboration with top-tier research institutions and industrial partners across Europe.
/li liFlexible working conditions and hybrid work environment.
/li liCompetitive remuneration aligned with seniority and expertise.
/li liPosition based in Rome.
/li /ul pbWe are looking for outstanding people willing to join our mission to change this industry and help to build a better world /b /p pAt Openchip Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas.
We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.
/p /p #J-*****-Ljbffr

📌 Physical Design Senior Engineer (Lazio)
🏢 Openchip & Software Technologies
📍 Lazio