ph3We Are /h3pSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their RD capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. /ph3You Are /h3pYou have spent over a decade turning RTL into working silicon, and you know that the difference between a SerDes IP that meets spec and one that actually tapes out comes down to decisions made during floor planning, not during signoff. /ppYou have taped out chips at 16nm or below. You write scripts because manual flows do not scale, and you speak timing signoff fluently enough to debug a failing path without waiting for translation. At Synopsys, you will work on 56G, 112G, and 224G PAM4/6 SerDes platforms that ship into real products. /ph3What You'll Be Doing /h3ulliDrive physical implementation of high-speed SerDes IPs and test chips from RTL to GDSII, including timing closure and physical signoff /liliLead a small team of engineers through implementation flows, setting technical direction and clearing tapeout blockers /liliDevelop timing constraints and design architectures that meet power, area, and performance targets on TSMC 16nm and below /liliCollaborate with front-end, analog, and CAD teams to resolve analog/digital interface challenges /liliAutomate implementation flows using Perl, Tcl, and Python across multiple process technologies /liliOwn chip-level integration and signoff for mixed-signal IPs before tapeout /li /ulh3The Impact You Will Have /h3ulliYour implementation decisions will determine whether SerDes IPs tape out on schedule and meet power and area targets /liliThe timing constraints you create will enable successful signoff across advanced process nodes /liliYour leadership will accelerate the team's ability to deliver complex mixed-signal IPs without last-minute rework /liliThe automation you build will reduce manual effort and improve consistency across future projects /liliYour technical judgment will shape how the team approaches low-power design and advanced node implementation /liliThe SerDes platforms you help deliver will power high-speed connectivity in AI, data center, and networking products worldwide /li /ulh3What You'll Need /h3ulliMSEE with 10+ years or BSEE with 12+ years in digital or physical design /liliExperience leading physical implementation through multiple project tapeouts /liliDeep knowledge of the full design cycle from RTL to GDSII, including chip-level integration /liliProven experience with TSMC 16nm or below, including low-power design techniques /liliStrong scripting skills in Perl, Tcl, or Python with CAD automation experience /liliSolid understanding of digital/mixed-signal verification flows and SOC integration /liliWillingness to travel internationally as required /li /ulh3Who You Are /h3ulliYou can spot the real bottleneck in a timing report and propose a fix that does not blow up area or power /liliYou push back on front-end teams if the RTL will create an unsolvable physical problem, and you can explain why /liliYou make decisions without waiting for perfect information because delay costs more than a well-informed judgment call /liliYou lead by setting clear direction and stepping in only when the team hits a blocker they cannot solve alone /liliYou treat automation as part of the job because you have seen what happens when manual flows meet tight schedules /li /ulh3The Team You'll Be Part Of /h3pYour recruiter will share more about the team structure and mission during the interview process. /ph3Rewards and Benefits /h3pWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. /p /p #J-18808-Ljbffr

📌 Principal R&D Engineer - Enterprise SerDes Physical Implementation (Italia)
🏢 Synopsys
📍 Italia