ph3Principal Verification Engineer /h3 h3Job Description /h3 h3Principal Verification Engineer /h3 pbSalary: /b Annual salary starting from €66,000, with the final offer depending on the candidate's experience and qualifications.
/p h3Description /h3 ponsemi's Power Management Division is seeking a Principal Verification Engineer with strong expertise in both block-level and SoC-level verification of integrated circuits.
The ideal candidate has hands?on experience with SystemVerilog, UVM and formal verification, and demonstrates a solid understanding of verification methodologies and coverage?driven approaches.
/p pYou will work in a globally distributed team environment, extracting design intent from specifications and translating it into comprehensive verification strategies and plans to ensure maximum functional and code coverage.
/p h3Responsibilities /h3 ul liDevelop SoC, subsystem, and block?level verification plans based on power management IC specifications.
/li liBuild, maintain, and enhance scalable and reusable verification environments.
/li liDrive verification quality to achieve target functional and code coverage metrics.
/li liPromote and implement innovative verification methodologies and technologies.
/li liEnsure comprehensive verification of both hardware and firmware components.
/li liAnalyze, debug, and root?cause verification failures efficiently.
/li liLead verification activities across the full lifecycle, from planning to silicon validation readiness,



with focus on pre?silicon quality.
/li liCollaborate closely with cross?functional teams and communicate effectively through coverage reviews, design/code reviews, and project updates.
/li /ul h3Qualifications /h3 ul liBSEE/MSEE (or equivalent) with 7–10+ years of relevant experience.
/li liStrong expertise in SystemVerilog and UVM, including vertical reuse methodologies.
/li liSolid knowledge of industry?standard EDA tools and verification flows.
/li liProven experience in debugging complex verification issues.
/li liHands?on experience with Assertion?Based Verification (SVA/PSL).
/li liUnderstanding of formal verification methodologies and their application to coverage closure.
/li liProficiency in scripting languages such as Python, Tcl, or C?shell.
/li liExperience in technical leadership and mentoring.
/li liGood understanding of analog and mixed?signal IC architectures and integration challenges.
/li /ul h3Nice to Have /h3 ul liExperience with power?aware verification (UPF/UCF).
/li liExposure to AI/ML techniques applied to verification.
/li liExperience in HW/SW co?verification environments.
/li liFamiliarity with requirements and project management tools (e.g., JAMA, JIRA).
/li liExperience with multi?phase switching regulators or power management systems.
/li /ul h3Benefits /h3 pMore details about our company benefits can be found here: /p /p #J-*****-Ljbffr

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