Synopsys Inc is seeking an experienced hardware engineer to drive physical implementation of high-speed SerDes IPs from RTL to GDSII, ensuring timing closure and signoff. You will lead a small team, set technical direction, and overcome tapeout blockers for 16nm and below processes.You will develop timing constraints and architectures to meet power, area, and performance targets, collaborating with front-end, analog, and CAD teams, while automating flows with Perl, Tcl, and Python.
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