Senior Engineer - Silicon Physical Design (Italy based) Apply for the Senior Engineer - Silicon Physical Design (Italy based) role at Axelera AI . Axelera AI is not your regular deep-tech startup. We are creating the next‐generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just four years we have raised a total of $120 million and built a world‐class team of 220+ employees (including 49+ PhDs with more than 40 000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our MetisTM AI Platform, which achieves a 3‐5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

As a Senior Silicon Physical Design Engineer at Axelera AI you will play a crucial role in developing cutting‐edge multi‐core in‐memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‐off and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution.

Perform synthesis, floorplanning, place and route, extraction, timing analysis and physical verification. Execute clock tree synthesis (CTS) and clock‐building techniques. Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics and analog IPs.





Utilise EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC and Calibre. Develop automation scripts in Python, Tcl or Perl. Debug and solve technical challenges related to physical design.

Collaborate with architecture, RTL and verification teams. 10+ years of experience in Physical Design (RTL to GDS). Expertise in synthesis, timing analysis and timing closure. Hands‐on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk and Calibre).

Experience in IP integration across various domains. Strong scripting skills (Python, Tcl or Perl). Fluent in English (spoken and written).

Experience in top‐level integration and I/O ring design. Knowledge of chip‐package‐board co‐simulation and packaging. Ability to influence design methodologies and tool flows.

Experience working with EDA vendors to resolve tool issues. Understanding of semiconductor device physics and multi‐domain design. This position is based in Italy (hybrid or remote setup). We also support relocation to Bologna, Florence or Milan for talent based abroad that is interested in this role. This is your chance to shape and be part of a dynamic, fast‐growing, international organisation.

We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. At Axelera AI we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. We welcome applicants from all backgrounds to join us in shaping the future of AI. Mid‐Senior level Full‐time Engineering and Information Technology

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