pINVENTVM is actively looking for a talented AMS Verification Engineer to join the design team. /ppbr / /ppIn this role, you will be responsible for verifying mixed-signal and analog/mixed-signal (AMS) integrated circuits by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success. You will work closely with analog and digital designers throughout the product development cycle. /ppbr / /ppstrongKey Responsibilities /strong /pp - Develop and execute verification plans for analog and mixed-signal IPs and SoCs /pp - Create, maintain, and enhance AMS verification environments using industry-standard methodologies /pp - Develop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languages /pp - Design testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionality /pp - Perform functional, corner, Monte Carlo, and regression simulations /pp - Collaborate with analog and digital design teams to identify, debug, and resolve functional issues /pp - Support integration and verification of analog IPs within larger digital or mixed-signal SoCs /pp - Analyze simulation results and communicate findings through clear technical reports /pp - Contribute to verification methodology improvements, automation,



and scripting /pp - Support silicon bring-up and correlation between simulation and laboratory measurements when required /ppbr / /ppstrongRequired Qualifications /strong /pp - Master's degree in Electrical Engineering, Electronics Engineering, or a related field /pp - Solid understanding of analog and mixed-signal circuit fundamentals, including: /ppbr / /pp br / Operational amplifiers /pp br / Comparators /ppbr / ADCs and DACs /pp br / PLLs (preferred) /pp br / Voltage regulators and references /pp br / Switched-capacitor circuits /ppbr / /pp - Experience with AMS simulation and verification tools (e.G., Cadence Virtuoso, Spectre, Xcelium) /pp - Knowledge of Verilog-AMS, Verilog-A, SystemVerilog, or Real Number Modeling (RNM) /pp - Familiarity with scripting languages such as Python, Tcl, Perl, or Shell /pp - Strong debugging and problem-solving skills /pp - Good communication skills and ability to work effectively in cross-functional teams /ppFluent in English /ppbr / /ppstrongDesirable Qualifications /strong /ppExperience with UVM-based verification environments. /pp - Knowledge of digital verification methodologies. /pp - Familiarity with mixed-signal modeling techniques and abstraction levels. /pp - Experience with low-power verification concepts. /pp - Understanding of CMOS device operation and semiconductor fundamentals. /ppbr / /ppAll INVENTVM positions offer a stake in the company equity that also entitles to receive dividends, competitive benefits, sustainable work logistics aimed at balancing personal life and project deadlines. /ppbr / /ppbr / /p

📌 Analog Mixed-Signal Verification Engineer (Roma)
🏢 Inventvm Semiconductor
📍 Roma