Senior Design Verification Engineer - Data Fabric SystemsLuxoft, RomaSalary: EUR 50,000 - 70,000As Design Verification Engineer, you will join a leading-edge team responsible for the verification of advanced interconnect systems in state‐of‐the‐art microprocessors. This role focuses on ensuring the functionality, performance, and reliability of high‐bandwidth data communication architectures.We are looking for a team player who is passionate about modern, complex processor architecture, digital design, and verification in general. You should possess strong analytical and problem‐solving skills, excellent communication, a willingness to learn, and readiness to accept challenges.ResponsibilitiesPerform pre‐Silicon Verification of next‐generation high‐performance Microprocessor designs and related IPs.Develop, document,



and execute verification test plans at the unit level of design hierarchy.Develop high‐level language testbench components including stimulus drivers, behavioral models, monitors, and checkers in SystemVerilog.Develop, simulate, and debug directed/random stimulus to ensure design functionality according to specifications.QualificationsMinimum of 5 years experience in Digital Design Verification.Strong skills with SystemVerilog and UVM; good skills with Verilog.Exposure to both maintaining an existing Verification Environment and creating one from scratch.Experience with functional verification tools such as VCS, Cadence, and Mentor Graphics.Experience working in a Unix/Linux environment.Seniority levelMid‐Senior levelEmployment typeFull‐timeIndustriesITmaktadırServices and IT Consulting#J-18808-Ljbffr

📌 Senior Design Verification Engineer - Data Fabric Systems - €50.000 - €70.000 A Year (Giuliano di Roma)
🏢 Luxoft
📍 Giuliano di Roma