ppDescrizione dell’offerta di lavoro /p pINVENTVM is actively looking for a talented AMS Verification Engineer to join the design team. /p pIn this role, you will be responsible for verifying mixed-signal and analog/mixed-signal (AMS) integrated circuits by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success. You will work closely with analog and digital designers throughout the product development cycle. /p h3Key Responsibilities /h3 ul liDevelop and execute verification plans for analog and mixed-signal IPs and SoCs /li liCreate, maintain, and enhance AMS verification environments using industry-standard methodologies /li liDevelop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languages /li liDesign testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionality /li liPerform functional, corner, Monte Carlo, and regression simulations /li liCollaborate with analog and digital design teams to identify, debug, and resolve functional issues /li liSupport integration and verification of analog IPs within larger digital or mixed-signal SoCs /li liAnalyze simulation results and communicate findings through clear technical reports /li liContribute to verification methodology improvements, automation,



and scripting /li liSupport silicon bring-up and correlation between simulation and laboratory measurements when required /li /ul h3Required Qualifications /h3 ul liMaster's degree in Electrical Engineering, Electronics Engineering, or a related field /li liSolid understanding of analog and mixed-signal circuit fundamentals, including: /li liOperational amplifiers /li liComparators /li liADCs and DACs /li liPLLs (preferred) /li liVoltage regulators and references /li liSwitched-capacitor circuits /li liExperience with AMS simulation and verification tools (e.g., Cadence Virtuoso, Spectre, Xcelium) /li liKnowledge of Verilog-AMS, Verilog-A, SystemVerilog, or Real Number Modeling (RNM) /li liFamiliarity with scripting languages such as Python, Tcl, Perl, or Shell /li liStrong debugging and problem-solving skills /li liGood communication skills and ability to work effectively in cross-functional teams /li /ul pFluent in English /p h3Desirable Qualifications /h3 ul liExperience with UVM-based verification environments. /li liKnowledge of digital verification methodologies. /li liFamiliarity with mixed-signal modeling techniques and abstraction levels. /li liExperience with low-power verification concepts. /li liUnderstanding of CMOS device operation and semiconductor fundamentals. /li /ul pAll INVENTVM positions offer a stake in the company equity that also entitles to receive dividends, competitive benefits, sustainable work logistics aimed at balancing personal life and project deadlines. /p /p #J-18808-Ljbffr

📌 Analog Mixed-Signal Verification Engineer (Lodi)
🏢 Inventvm Semiconductor
📍 Lodi