13 set
|
Inventvm Semiconductor
|
Pavia
13 set
Inventvm Semiconductor
Pavia
INVENTVM Semiconductor is seeking an experienced AMS Verification Engineer to join our design team in Italy. You will verify mixed-signal ICs by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success.
You will collaborate with analog and digital designers throughout the product development cycle, develop models using Verilog-A/Verilog-AMS, and drive simulations including Monte Carlo and regression tests to validate functionality.
J-18808-Ljbffr
📌 AMS Verification Engineer (Pavia)
🏢 Inventvm Semiconductor
📍 Pavia