Overview
In this Staff role, you will design and verify high-speed analog SerDes sub-blocks, driving reliability and performance in silicon. You’ll collaborate with System Architecture, Digital Design, and Analog Physical Design teams to translate specifications into robust, silicon-ready blocks. You’ll lead analog sign-off activities and influence architectural choices to meet design goals. This position offers scope to shape cutting-edge mixed-signal tech within a global semiconductor leader.

Retribuzione / Benefits
- comprehensive total rewards package
- hybrid workplace

Responsabilità
- Design and verify analog circuits for high-speed SerDes sub-blocks (deserializers, serializers, drivers, CTLE, Slicers)
- Perform analog sign-off activities (EMI, aging, reliability checks)
- Collaborate with System Architecture to define/refine analog specs
- Evaluate and select optimal architectural solutions to meet specifications
- Partner with Digital Design to ensure proper control/integration of analog blocks




- Coordinate with Analog Physical Design for robust high-frequency layout
- Engage with Verification teams to ensure silicon-ready designs

Requisiti fondamentali
- Master’s degree in Electrical/Electronic Engineering or related field
- 5+ years of experience in analog design for high-speed SerDes IPs
- Knowledge of SerDes sub-block design (deserializers/serializers, drivers, CTLE, slicers)
- Experience with Analog Design Tools (Virtuoso, Spectre, and others)
- FinFET technologies experience is a strong advantage
- Strong collaborative mindset and cross-functional teamwork
- Fluency in English (mandatory)
- cross-functional collaboration
- eagerness to learn and develop technical expertise
- team-oriented mindset
- SerDes sub-block design
- CTLE and slicer design
- analog circuit design for high-speed blocks

📌 Staff Analog Mixed-Signal Design Engineer (Pavia)
🏢 Infineon Technologies
📍 Pavia