pams OSRAM in Italy seeks a Technical Leader for architecture and RTL development of high‑speed digital subsystems in communication ICs and mixed‑signal SoCs. You will define digital subsystem architectures and guide RTL integration. /ppIdeal candidates hold MSc/PhD in Electrical Engineering with 10+ years in digital IC design, RTL (Verilog/SystemVerilog), and experience with high‑speed interfaces (UCIe, PCIe). /p #J-18808-Ljbffr
📌 Senior RTL Architect & Tech Lead - High-Speed Digital ICs (Cerano)
🏢 Ams Italy
📍 Cerano
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