22 set
|
Altro
|
Corte Palasio
22 set
Altro
Corte Palasio
ams OSRAM is seeking aTechnical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products. The role involves defining digital architectures and leading RTL development with a focus on timing, synthesis, and integration.
Candidates should have MSc/PhD in Electrical Engineering and 10+ years of digital IC design experience, with proficiency in Verilog/SystemVerilog and experience with high-speed interfaces such as
#J-18808-Ljbffr
📌 Senior Digital Design Architect, High-Speed ICs (Corte Palasio)
🏢 Altro
📍 Corte Palasio