ams Italy S.r.l. in Voghera, Lombardy, seeks a Technical Leader to own architecture and RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs.
The role requires a strong background in Verilog/SystemVerilog and leadership of architecture and integration efforts.
Applicants should have MSc or PhD in Electrical Engineering and 10+ years of digital IC design experience, with knowledge of interfaces such as UCIe or PCIe considered an advantage.
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