pams OSRAM is seeking a technical leader for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoCs. You will define digital architectures and lead RTL design using Verilog/SystemVerilog, guiding integration and design reviews at our Castellar site in Piemonte. /ppThe role requires 10+ years of digital IC design, expertise in synthesis and timing analysis, and experience with high-speed interfaces; FinFET/FD-SOI know-how is a plus. /p #J-18808-Ljbffr
📌 Senior Digital IC Architect & RTL Lead (High-Speed) (Castellar)
🏢 Ams Italy
📍 Castellar
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