pams Italy S.r.l. is seeking a Technical Leader to own architecture and RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs.
You will define architectures and lead RTL design, ensuring integration and adherence to quality standards.
/ppThe role requires 10+ years of digital IC design experience, strong Verilog/SystemVerilog skills, and expertise in high-speed interfaces and timing analysis.
FinFET/FD-SOI experience is preferred.
/p #J-*****-Ljbffr
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