Fpga Design Engineer – Dsp & High-Speed Interfaces (Lazio)

Fpga Design Engineer – Dsp & High-Speed Interfaces (Lazio)

21 set
|
FAE Technology
|
Lazio

21 set

FAE Technology

Lazio

We offer: Contract type and compensation will be defined based on the candidate's experience.
We are looking for a talented and experienced
FPGA Designer
to join our R&D; team.
The successful candidate will be responsible for the
architecture, development, and integration of advanced firmware on state-of-the-art FPGA/SoC technologies
.
The ideal candidate has strong expertise in the hardware implementation of
digital signal processing (DSP) algorithms
and in managing
ultra-high-speed serial interfaces
, working in high-performance application environments (e.g. Telecommunications, Aerospace, Defense, Automotive, or Industrial Automation).
The role involves:
Firmware Architecture and Development:
Design and implement complex firmware modules in VHDL, Verilog, or SystemVerilog.
Radio and Video Signal Processing (DSP):
Translate, optimize, and implement in silicon mathematical and filtering algorithms (e.g. FIR/IIR filters, FFT, modulations, embedded control loops, RFSoC algorithms, video processing chains) derived from high-level models.
High-Speed Interfaces:
Design, configure, and validate high-performance serial interfaces (PCIe, ******G Ethernet, JESD204B/C, Aurora, DDR4/DDR5, HDMI, DisplayPort).
Simulation and Verification:
Create advanced testbench environments (UVM, SystemVerilog, or using standard tools) for functional verification and pre- and post-synthesis simulation.
Timing Closure:
Manage complex timing constraints (SDC/XDC), analyze synthesis reports, and optimize placement and routing (Place & Route) to ensure timing closure at high clock frequencies.




Integration and Laboratory Debugging:
Work closely with the Hardware team on electronic board bring-up, using advanced instrumentation such as oscilloscopes, logic analyzers, and bus analyzers.
Documentation:
Prepare project technical documentation (architecture, test specifications, registers, and control interfaces).
Requirements:
HARD SKILLS
Education:
Master's Degree in Electronic Engineering, Telecommunications Engineering, Computer Engineering, or equivalent.
Experience:
At least 3–5 years of experience in firmware development on FPGA architectures.
Reference Platforms:
In-depth knowledge of leading SoC/FPGA platforms (e.g. AMD/Xilinx UltraScale+, Zynq, Versal, or Intel Stratix/Agilex platforms).
Hardware Programming Languages:
Full proficiency in VHDL and/or Verilog/SystemVerilog.
Development Tools:
Proficiency in native IDE development environments (e.g. Vivado Design Suite, Quartus Prime) and simulation tools (e.g. ModelSim, QuestaSim).
Algorithmic Modeling:
Proficiency in MATLAB/Simulink and high-level synthesis tools (HLS – High-Level Synthesis).
Signal Integrity:
Basic understanding of issues related to high-speed PCB layout (Signal Integrity and Power Integrity).
SOFT SKILLS
Problem Solving:
Analytical and methodical approach focused on the rapid identification and resolution of complex hardware bugs.
Teamwork:
Ability to collaborate within multidisciplinary teams (System Engineers, Hardware Designers, Embedded Software Engineers).
Languages:
Excellent command of technical English, both written and spoken.
#J-*****-Ljbffr

📌 Fpga Design Engineer – Dsp & High-Speed Interfaces (Lazio)
🏢 FAE Technology
📍 Lazio

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