pams Italy S.r.l. in Desio, Lombardy, seeks a technical leader for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed?signal SoCs.
/ppYou will define digital subsystem architectures and lead RTL development and integration.
Responsibilities include driving design reviews, ensuring quality standards, supporting verification teams, and mentoring design engineers, with a focus on Verilog/SystemVerilog and high-speed interfaces like PCIe/UCIe and related /p #J-*****-Ljbffr
📌 Principal High-Speed Digital Rtl Architect (Desio)
🏢 Ams Italy
📍 Desio
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