pams Italy S.r.l. seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs.
You will define architectures, lead RTL development, and drive design reviews while mentoring engineers.
/ppRequirements include MSc/PhD in Electrical Engineering and 10+ years in digital IC design with RTL (Verilog/SystemVerilog).
Knowledge of high-speed interfaces like UCIe/PCIe is a plus.
/p #J-*****-Ljbffr
📌 Senior Rtl & High-Speed Digital Ic Architect (Bardi)
🏢 Ams Italy
📍 Bardi
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