ams OSRAM in Italy seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoCs. You will define architectures, lead RTL design and integration, drive design reviews, and mentor engineers, collaborating with verification and implementation teams. Candidates should have MSc/PhD in EE and 10+ years of experience; familiarity with PCIe/UCIe is a plus; CMOS FinFET/FD-SOI experience is required.
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📌 Senior RTL Design Architect – High-Speed Digital ICs (Sant'Alessio con Vialone)
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📍 Sant'Alessio con Vialone
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