28 set
|
Nokia
|
La Spezia
pNokia seeks an experienced ASIC physical design engineer to implement floorplanning, place route, and power/clock distribution for submicron nodes. You will work with a hardware/RTL team to translate designs into silicon and optimize flows. /ppThis role emphasizes collaboration across cross-functional teams, verification rigor, and automation, with hybrid work and strong learning opportunities in latest nodes and tools. /p #J-18808-Ljbffr
📌 SoC Physical Design Engineer: Floorplanning, Timing & Automation (La Spezia)
🏢 Nokia
📍 La Spezia