In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and design methodologies. The opportunity centers on delivering best-in-class silicon while learning the latest nodes and tools. You will contribute to a mission-driven environment that values automation and rigorous verification.Si candidi (facendo clic sul pulsante apposito) dopo aver controllato tutte le informazioni di lavoro riportate di seguito.Flexible and hybrid working schemesParental leave (90 days) with return optionLife insurance for employeesWell-being programs for mental and physical healthParticipation in Nokia Employee Resource Groups (NERGs)Career development and coaching/mentoringPerform floorplanning, place & route, and power/clock distribution for blocks and full chipsExecute physical verification, IR/EM analysis,



and timing closure at block and chip levelCollaborate with logic designers and hardware teams on feasibility studies and design trade-offsEvaluate IP vendors, process nodes, and provide actionable recommendationsDevelop PD methodologies and automation scripts for steps from Synthesis to GDSIIConduct static timing analysis, create timing constraints, validate critical paths, and sign off timing3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodesSolid knowledge of RTL to GDSII and underlying xysqume IC design conceptsExperience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, RedhawkScripting experience in TCL, Python or PerlBachelor's degree or higher in Electrical/Electronics and Communication/VLSI/MicroelectronicsStrong collaboration with cross-functional teamsteam collaborationanalytical mindsetproblem solvingFloorplanning and placement/routingSoC Physical Design Engineer livorno, toscana, it#J-18808-Ljbffr

📌 Soc Physical Design Engineer (Magliano in Toscana)
🏢 Nokia
📍 Magliano in Toscana