06 ott
|
Fondazione Chips-IT
|
Cascina
06 ott
Fondazione Chips-IT
Cascina
FONDAZIONE CHIPS-IT seeks a CAD & EDA Flow Engineer to manage and optimize the EDA infrastructure for advanced SoC design up to tape-out.
You will liaise with Cadence, Synopsys and Siemens, install and maintain PDKs across digital, analog and RF workflows, and support foundries for DRC/LVS and tape-out readiness. The role is based in Italy, with options between Pavia and Bologna.
You will also create internal trainings and documentation to accelerate design teams and evolve design flows.
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📌 EDA & CAD Flow Engineer for SoC Tapeout (Cascina)
🏢 Fondazione Chips-IT
📍 Cascina