04 ott
|
Ams Italy
|
Vigevano
04 ott
Ams Italy
Vigevano
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is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products.You will define architectures, lead RTL design and integration, and drive design reviews to ensure quality.The ideal candidate has MSc or PhD in Electrical Engineering with 10+ years of digital IC design xysqume experience, strong Verilog/SystemVerilog skills, and hands-on experience with high-speed interfaces and timing#J-*****-Ljbffr
📌 Senior Hs Digital Design Engineer – Soc Rtl Lead (Vigevano)
🏢 Ams Italy
📍 Vigevano