Overview
As a Design Engineer for DFT in the NVEG group, you will design, optimize, and validate DFT architectures for NAND Flash memory.
You will partner with cross?functional teams to boost testability, quality, cost efficiency, and speed to market, applying DFT strategies across digital logic, custom circuits, firmware, and silicon validation.
You'll define test strategies, analyze coverage, and develop validation methods at block and chip level.
This role offers a chance to shape testability for next?gen NAND devices and contribute to manufacturing excellence.
Retribuzione / Benefits
meal vouchers
corporate welfare
remote working days
supplementary health insurance
life coverage
Employee Assistance Program
Responsabilità
Define, implement, and optimize DFT architectures and test strategies for NAND designs (digital and custom blocks)
Analyze testability and coverage to meet quality, reliability, and manufacturability requirements
Develop and validate test sequences, NAND test algorithms,



and verification methodologies at block and chip levels
Collaborate with cross?functional teams and Product Engineering to support DFT integration, silicon bring?up, debugging, and ramp
Document DFT architectures, methodologies, and results to continuously improve test quality and efficiency
Requisiti fondamentali
M.S. in Electrical Engineering or Ph.D. in Electrical Engineering/Electronics or related field
Strong understanding of digital design, verification, and test/DFT principles
Proficiency in C/C++ and Python
Hands?on experience with simulation and validation methodologies for digital or mixed?signal designs
Strong problem?solving and communication skills for cross?functional collaboration
cross?functional collaboration
strong communication
problem solving
DFT architectures and test strategies
digital design and verification
test/validation methodologies

📌 Engineer, Design (Avezzano)
🏢 MICRON
📍 Avezzano