We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are
You have spent your academic career and early professional years building an understanding on different aspects of either analog or digital design and have curiosity of how high-speed communication systems actually work, not just in theory but in the messy reality where channel loss, jitter, non linearities, DSP sizing, LMS convergence and impedance mismatches determine whether a link closes or fails. You strive for holistic understanding of complex systems and you believe the way to create at optimized product is to capture the interaction between analog circuits, digital logic, and algorithms in a single coherent simulation environment.

Collaboration comes naturally to you.

When a model behaves differently than the circuit description suggests you hunt for the truth. You sit with the analog designer who owns the amplifier block, understand the frequency response trade-offs, and update your MATLAB representation until it reflects reality. You are comfortable presenting technical results in gate reviews and defending your sign-off decisions when someone questions your assumptions.

You care about closing the loop between simulation and silicon. When lab measurements do not match your predictions, you treat it as a puzzle and get into the lab to solve it. At Synopsys, you will work on leading edge SerDes IP that powers PCIe and Ethernet interfaces across the semiconductor industry.

What You'll Be Doing

Build and update MATLAB models of SerDes analog and DSP blocks in cooperation with the system architect, translating circuit designs into accurate system-level representations

Own system sign-off and performance evaluation for SerDes products, presenting results in gate reviews and carrying the outcome into successful product releases

Challenge and update models to close simulation-to-silicon correlation, working directly with the post-silicon validation team to understand lab data and refine predictions





Work with analog and digital engineers to assess how block and algorithm choices affect link quality and system performance across the signal chain

Check algorithm behavior against Ethernet and PCIe specifications, ensuring product operation aligns with compliance requirements

Develop new algorithms required for product operation or performance improvements, translating system-level needs into implementable solutions

Script and automate simulation runs, including AI-assisted flows, to improve efficiency and enable faster design iteration

Support lab-data analysis and debug on existing products, helping validation teams understand performance issues and root causes

The Impact You Will Have

Ensure SerDes IP meets performance targets before release, reducing risk of costly silicon respins and delays

Provide the holistic system view that brings analog, digital, firmware, and validation disciplines into a unified understanding of product performance

Shape next-generation SerDes architectures by identifying performance bottlenecks and optimization opportunities early in the design cycle

Improve simulation-to-silicon correlation across the product portfolio, making future development cycles faster and more predictable

Enable successful product releases by catching specification compliance issues and performance gaps before tapeout

Influence how high-speed interfaces perform in networking, AI, and data center applications used by customers worldwide

Act as the technical integration point where contributions from multiple engineering teams are evaluated, validated, and signed off together

What You'll Need

Masters degree in Electrical Engineering, Electronics Engineering, or a related field

Relevant experience, such as: internships, thesis work, or early industry experience in communications, circuits, or signal processing is a strong plus

Proficiency in MATLAB or C++ for system modeling, scripting, and automation

Solid understanding of analog and digital circuit fundamentals, including SerDes architectures, channel loss and equalization, amplifier frequency response, reflections and impedance matching, jitter analysis, and DAC/ADC architectures and performance metrics





Basic understanding of optical communication systems and photonics

Fluent English, including the ability to present technical topics and answer audience questions clearly

Familiarity with Linux and Bash, Python, prior SerDes or communications-modeling projects, or lab measurement experience is a plus

Who You Are

You ask the right questions when a model behaves differently than the circuit description suggests, and you do not move forward until the gap is resolved

You are collaborative by instinct, working closely with the system architect and with analog, digital, and algorithm designers to ensure model accuracy

You can present system sign-off results in a gate review, explain your methodology, and defend your conclusions when stakeholders challenge your assumptions

You are organized and persistent in problem-solving, managing multiple modeling tasks and simulation runs without losing track of details that affect accuracy

You communicate clearly across engineering domains, translating between analog circuit behavior, digital implementation constraints, and algorithm performance trade-offs

You treat simulation-to-silicon correlation as a puzzle worth solving, diving into lab data with the validation team to understand why predictions and measurements diverge

The Team You'll Be Part Of
You will join the SerDes system team in Pavia, which develops and maintains the link model for high-speed serial links compliant with the latest PCIe and Ethernet specifications. The team includes system architects and works closely with R&D; functions across analog design, digital design, firmware design and validation, and hardware engineering. This team is the ultimate owner of system architecture and performance, ensuring the quality of existing products and shaping next-generation devices. The role sits at the center of the disciplines that build a complex system, with the goal of making sure the pieces work together to deliver the functionality and performance of the whole system.

Role Details

Location: Pavia, Italy

Working Model: Hybrid

Expected Start Date: December 2026

Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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📌 SerDes System Design Engineer (Pavia)
🏢 Synopsys
📍 Pavia