VisLab (an Ambarella Inc. company) in Parma, Italy seeks a Sr. ASIC Design Engineer to develop micro‑architecture for a next‑gen computer vision processor and implement modules in Verilog/SystemVerilog for SOCs. You will optimize timing, area and power while advancing front‑end methodologies and tool flows. The role requires a Master’s in Electrical Engineering and 0–4 years of relevant experience with strong HDL skills and scripting ability in Python or Perl. #J-18808-Ljbffr
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