The Role
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As a Functional Verification Principal Engineer, you will be interfacing with architecture, de-sign, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

The Role

As a Functional Verification Principal Engineer, you will be interfacing with architecture, de-sign, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

Key Responsibilities

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- Reading and analysing the system requirements and architecture requirement documents.

- Developing detailed Test and Coverage plans based on the Architecture and Micro-architec-ture.

- Developing Verification Methodology, ensuring scalability and portability across environ-ments.

- Developing Verification environment development and maintenance in SystemVeri-log/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.

- Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regres-sions and Debug of the test failures.

- Using the standard tools and flows of the verification process (Simulators, Coverage Analyz-ers, Unix, Continuous Integration, Bug Tracking, …).





- Create and execute testcases to verify the functionality, performance, and robustness in em-bedded C and SV.

- Identify, isolate, and debug issues found during verification, leveraging simulation and debug-ging tools to root-cause failures and drive resolution with design and architecture teams.

- Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verifi-cation activities.

- Organize work and deliverables between skills, internal and external teams.

- Mentoring and training the next generation of verification engineers.

- Coordinating functional verification teams.

Required Skills And Experience

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- Master Degree in relevant field.

- Min 15 years of experience in relevant field of Verification of complex SoC or IP

- Experience in

- SystemVerilog/UVM

- SystemC/C++

- Experience in Constrained random, Functional Coverage development, design debug.

- Experience in Formal Verification, UPF.

- Experience in HW-SW co-verification and simulation.

- Some previous experience in Firmware based verification is a good to have.

- Some knowledge of scripting languages like Bash/Perl/Python.





- Use of verification management tools.

- Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.

- Good level of English, both written and spoken is mandatory.

Preferred Qualifications

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- Experience in Firmware-based verification.

- Knowledge in metrics-driven verification.

- Insights of NOC and other IPs or standard peripherals like PCIe, DDR, HBM …

Soft Skills

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- Team player, able to work with multiple cultures both on site and remotely.

- Autonomous and flexible is mandatory.

- Strong Leadership and Communication abilities.

What do we offer?

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- Join an innovative team and experience company growth.

- We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers.

- Enjoy a hybrid work environment.

- We also offer flexible schedule.

- We offer a remuneration that values your experience.

- The position will have the base in Rome.

We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. xysqume We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential - regardless of race, gender, ethnicity, sexual orientation, or gender identity.

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📌 Principal Functional Verification Engineer (Roma)
🏢 Openchip & Software Technologies
📍 Roma