20 ott
|
Nokia
|
Pianazza
Nokia seeks an experienced ASIC physical design engineer to implement floorplanning, place & route, and power/clock distribution for submicron nodes.
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You will work with a hardware/RTL team to translate designs into silicon and optimize flows. xkiyazw
This role emphasizes collaboration across cross-functional teams, verification rigor, and automation, with hybrid work and strong learning opportunities in latest nodes and tools.
📌 SoC Physical Design Engineer: Floorplanning, Timing & Automation (Pianazza)
🏢 Nokia
📍 Pianazza