Overview

As an SoC Physical Implementation Engineer in Infineon's Research & Development team, you join a dynamic group responsible for delivering digital physical design for advanced SoCs. You will own P&R; work packages, drive timing closure, and collaborate across digital and analog teams to ensure a smooth RTL-to-GDS flow. This role offers hands-on impact on chip-level optimization and design verification in a fast-paced, cross-functional environment. You will work on innovative, green-energy and IoT solutions that scale with the company's mission.

Retribuzione / Benefits

- comprehensive total rewards package
- salary and premio structure
- employee development
- international, cross-functional team environment

Responsabilità

- Own Digital Physical Design work packages (floorplanning, partitioning, placement and routing)
- Optimize timing, power, and area to design specifications
- Achieve timing closure and perform verification and sign-off
- Develop P&R; scripts to automate development flows
- Collaborate with digital design/synthesis and analog layout teams in a mixed digital/analog flow
- Participate in design reviews, FMEA, and generate design reports




- Estimate effort, plan work packages, and interface with project team

Requisiti fondamentali

- Degree in Electrical/Electronic Engineering or equivalent field with knowledge of microelectronic devices and digital circuit design
- ≥3 years' experience in implementing SoC designs from RTL to GDS, UNIX preferred
- Solid experience in RTL-to-GDS flow: synthesis, P&R;, STA and sign-off checks in sub-micron tech with Synopsys or Cadence tool chains
- Experience with physical design work-package planning, including effort estimation and risk management
- Strong scripting skills (TCL, Python and/or Perl); DFT experience a plus
- Proven experience with CAD tools such as Innovus or Genus
- Fluent in English
- Strong analytical and problem-solving abilities
- Team player in international, cross-functional environments
- creative and open-minded approach to drive innovation and collaboration
- Floorplanning, Partitioning, Placement & Routing
- Timing Closure, STA, clock/data integrity
- RTL to GDS flow

📌 SoC Physical Implementation Engineer (Padova)
🏢 Infineon Technologies
📍 Padova