Your tasksTechnical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC productsDefine digital subsystem architecturesLead RTL development and integrationDrive design reviews and quality standardsSupport verification and implementation teamsMentor design engineersWho we are looking forMSc or PhD in Electrical Engineering10+ years digital IC design experienceRTL design (Verilog/SystemVerilog)High-speed digital IC design
📌 Principal Hs Digital Design Engineer (D/M/F) (Pavia)
🏢 Ams Italy
📍 Pavia
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