Your tasksbr/br/- Technical expert and recognized authority for physical implementation of high-speed digital and mixed-signal ICsbr/br/- Lead place-and-route implementation from synthesis results through PnR to sign-off and tape-outbr/br/- Define, deploy, and maintain digital backend methodologies, flows, and best practicesbr/br/- Drive timing closure, power, performance, area (PPA), signal integrity, EM/IR and physical verification strategiesbr/br/- Mentor and develop engineers within the digital backend communitybr/br/- Lead EDA tool evaluations, methodology improvements, and flow automation initiativesbr/br/- Support technology enablement for advanced CMOS nodes including FinFET and FD-SOIbr/br/- Provide technical leadership across multiple projects and business unitsbr/br/- Act as interface to foundries, EDA vendors, and methodology teamsbr/br/- Drive continuous improvement of backend design efficiency and qualitybr/br/Who we are looking forbr/br/- MSc or PhD in Electrical Engineering, Microelectronics,



or related fieldbr/br/- 10+ years of experience in digital physical implementation and backend designbr/br/- Proven expertise with industry-standard physical design tools and flows (Cadence EDA flow preferred)br/br/- Strong knowledge of floorplanning, placement, CTS, routing, STA, physical verification, power integrity, and signal integrity analysisbr/br/- Extensive experience with timing closure and sign-off methodologiesbr/br/- Experience with high-speed interfaces such as UCIe, PCIe, DDR, SerDes, USB, MIPI, or similar protocols is highly desirablebr/br/- Experience driving methodology development and engineering best practices across multiple projectsbr/br/- Strong communication, collaboration, mentoring, and technical leadership skillsbr/br/- Ability to work independently and influence technical decisions at organizational levelbr/br/ams OSRAM is an Equal Employment Opportunity Employer. Diversity, equity and inclusion is strongly established in our corporate culture and we firmly believe it makes us more successful as a company. All qualified applications will receive consideration for employment regardless of ethnic, national or social origin, gender, gender identity, sexual orientation, color, religion, age, physical and mental abilities.

📌 Principal HS Digital Place & Route Engineer (d/m/f) (Pavia)
🏢 Ams Italy
📍 Pavia