27 ott
|
VisLab (an Ambarella Inc.
|
Bologna
27 ott
VisLab (an Ambarella Inc.
Bologna
VisLab, an Ambarella Inc. company, in Parma, Italy, seeks a Sr. ASIC Design Engineer to develop micro-architecture for a next-generation computer vision processor and to implement Verilog/SystemVerilog modules for cutting-edge SOCs.
Prima di candidarsi per questo ruolo, la preghiamo di leggere le seguenti informazioni su questa occasione, riportate di seguito.
The ideal candidate holds a Master’s in Electrical Engineering with up to 4 years of experience and has a strong background in VLSI/ASIC design, design verification, and scripting (Python/Perl). xbvzest Knowledge in image/video processing and ML is a plus.
📌 Senior ASIC Design Engineer (Bologna)
🏢 VisLab (an Ambarella Inc.
📍 Bologna