pIn this role you will help design and implement advanced digital subsystems for automotive and industrial electrification. You will collaborate with architects, verification engineers, and cross-functional teams to define digital architecture and ensure robust RTL in SystemVerilog. You will address performance, power, area, safety, and testability trade-offs and drive design quality through verification and sign-off readiness. This position offers impact across mixed-signal projects, reuse of digital IP, and contribution to safety-compliant automotive developments. You will work in a global, collaborative environment focused on delivering high-quality mixed-signal solutions at scale. /pulliequal pay commitment /liliannual incentive opportunities /liliequity /lilicompetitive benefits package /liliDevelop RTL designs for complex digital blocks and subsystems using SystemVerilog/Verilog /liliContribute to digital architecture definition with senior designers and system architects /liliAnalyze design trade-offs for performance, power, area, safety, and testability /liliImplement clocking, reset, and power management strategies /liliSupport IP integration and subsystem-level development /liliPerform RTL verification activities including simulation, lint, CDC, and synthesis checks /liliCollaborate with digital verification engineers for coverage and quality /liliSupport timing closure and implementation activities /liliParticipate in design reviews and sign-off readiness /liliSupport silicon bring-up, debugging,



characterization, and root-cause analysis /liliWork within mixed-signal project teams and promote reuse of digital IPs and methodologies /liliContribute to requirements definition and feasibility analysis /liliSupport multiple development phases from concept through production release /liliFollow automotive standards for functional safety and quality /liliProvide technical guidance to less experienced engineers /liliCollaborate across international RD sites /liliMaster's degree in Electrical Engineering, Electronics Engineering, or equivalent /liliMinimum 7 years of experience in digital IC design /liliStrong experience with RTL development using SystemVerilog/Verilog /liliExperience with synthesis, timing constraints, and digital implementation flows /liliUnderstanding of CDC, reset strategies, and low-power design concepts /liliFamiliarity with DFT fundamentals and design-for-test methodologies /liliExperience in mixed-signal IC development environments /liliKnowledge of digital verification methodologies and simulation-based verification /liliExperience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA) /liliFluent written and spoken English /liliTeam collaboration /liliCross-functional communication /liliMentoring and knowledge sharing /liliSynthesis and timing constraints /liliDigital implementation flows /li /ulpSenior Digital Design Engineer • varese, lombardia, it /p #J-18808-Ljbffr

📌 Senior Digital Design Engineer (Varese)
🏢 NXP Semiconductors
📍 Varese