h3bAbout Huawei /b /h3pHuawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices.
With integrated solutions across four key domains – telecom networks, IT, smart devices, and cloud services – bwe are committed to bringing digital to every person, home and organization for a fully connected, intelligent world.
/b /ppAt Huawei, innovation focuses on customer needs.
We invest heavily in basic research, concentrating on technological breakthroughs that drive the world forward.
We have more than b200,000 employees /b, of bwhich 55% are employed in RD /b, and we operate in more than 170 countries and regions.
/ppHuawei invests more than b20% of revenues in RD /b every year: in the past 10 years our total bRD investments exceed 150B USD /b.
/ppBy the end of ****, Huawei held b+150.000 active patents /b.
/ppCentral Hardware Engineering Institute (CHEI) at bHuawei Milan Research Center /b focuses on advanced hardware technologies for next-generation ICT systems, with strong emphasis on high-speed interconnects, power integrity (PI), signal integrity (SI), and system-level performance optimization.
The team develops both engineering solutions and internal methodologies/tools to enable robust, scalable hardware design.
/ppWe are looking for a: /ppSenior Engineer – Silicon-to-System Power Delivery Integrity /ph3bThe opportunity /b /h3pYou will lead research and methodology development in power delivery and power integrity, focusing on the interactions between SoC silicon power characteristics and package to board power delivery architectures.
This role centers on developing custom modeling methodologies,



computational frameworks and cross-layer optimization strategies to address SoC power delivery challenges in next generation high performance computing platforms.
/ph3bKey Responsibilities /b /h3pbSoC Power Characterization: /b Research and analyze silicon power characteristics, dynamic current profiles and voltage droop budgets to define target impedance and guide board level design.
/ppbDie to System PDN Modeling: /bDevelop and apply advanced PDN/PI modeling methodologies that incorporate silicon power delivery characteristics and transient load behavior to evaluate voltage regulation, die-package-board resonances and opportunities for system-level architectural improvements.
/ppbSoC Workload-Driven Optimization /b: Define and optimize board-level PDN architectures, decoupling strategies, and VRM design based on SoC workload characteristics, balancing PI performance, design margins, PCB area, and cost.
/ppbChip to system framework research: /b Develop and validate computational frameworks integrating SoC load behavior with system level PDN models, and investigate emerging power delivery technologies to identify feasible research directions and architectural improvement /ph3bRequired Qualifications /b /h3ullipM.S.
with 6+ years' industry experience or Ph.D. with 3+ years' industry experience in Electrical Engineering, (or a related field) with background on system-level PI/PDN design.
/p /lilipStrong understanding of Silicon to system power architecture, including SoC power characteristics,



transient current behavior, voltage drop constraints and their impact on package and board level PDN design.
/p /lilipExperience developing PI methodologies, PDN models, transient analysis workflows and lab correlation.
/p /lilipProficiency with industry-standard simulation tools and scripting languages for custom modeling and design automation.
/p /li /ulh3bNice to have /b /h3ullipExperience with AI, HPC or datacenter platforms involving high power density and large transient current demands.
/p /lilipFamiliarity with SoC power management techniques, including dynamic voltage and frequency scaling.
/p /lilipKnowledge of integrated voltage regulators architectures (IVRs), high frequency VRMs, advance power delivery architectures and high bandwidth power delivery control loops.
/p /lilipExperience developing or validating chip/package/board electrical models and applying computational methods to automate system-level PI.
/p /li /ulpWhile we have outlined a set of requirements, we value transferable skills and diverse experiences.
If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background makes you a strong candidate.
/ph3bWhat We Offer /b /h3pWe offer you an exciting professional career in one of the leading and fastest growing multinational telecommunication companies, challenging work and a competitive salary package.
Personal development is ensured through many training opportunities in Western Europe and abroad.
/ppWe offer a gross annual salary typically ranging from €65,000 to €80,000 determined according to objective criteria such as professional experience, competencies, and seniority.
Employ

📌 Senior Engineer – Silicon-To-System Power Delivery (Bardi)
🏢 HUAWEI TECHNOLOGIES ITALIA
📍 Bardi