Overview In this role you will own the development of NAND Flash logic features, from concept to RTL, verification and post-silicon validation. You will bridge architecture, firmware, datapath, analog and test teams to deliver robust digital implementations across technology generations. You’ll support silicon bring-up, validation and learning while leveraging AI-enabled workflows to boost productivity. This position offers collaboration with cross-functional teams to scale performance, power, and reliability in memory products. Retribuzione / Benefits
* meal vouchers
* corporate welfare
* remote working days
* supplementary health insurance
* life coverage
* Employee Assistance Program Responsabilità
* Own end-to-end development of logic features from architecture through RTL and validation
* Translate system/firmware requirements into micro-architecture specs and digital implementations
* Develop RTL and drive block/subsystem/full-chip verification including coverage and post-layout validation
* Collaborate with cross-functional teams to define interfaces and optimize performance, power and reliability




* Support silicon bring-up, debugging and root-cause analysis to improve yield and ramp
* Leverage AI-assisted engineering tools for code generation, review, debug and documentation
* Apply AI-enabled analysis to large design, verification, or silicon datasets
* Identify opportunities to automate repetitive tasks using AI technologies
* Integrate AI automated workflows into engineering activities Requisiti fondamentali
* M.
S. in Electrical Engineering, Electronics, or related field
* Strong experience in digital logic design and verification for complex SoCs or memory products
* Hands-on RTL design, gate-level verification and simulation methods
* Solid understanding of system-level and micro-architectural design trade-offs (performance, power, reliability)
* Strong communication and problem-solving skills in global, multi-functional teams
* strong communication
* problem-solving
* team collaboration
* RTL design
* gate-level verification
* simulation methodologies

📌 SR ENGINEER, DESIGN (Avezzano)
🏢 MICRON
📍 Avezzano